Running the HDL designs in ALINT-PRO comprises of two key workflows: design entry and linting. The rules cover typical coding mistakes, inconsistent coding style and limited code re-use, sub-optimal synthesis, synthesis vs simulation mismatches, non-portable coding practices, improper clock and reset networks, unsynchronized clock domain crossings, and many more topics. The primary purpose of applying ALINT-PRO is the Design Rule Checking (DRC) for the RTL code written in VHDL, Verilog and SystemVerilog design subset before running the logic synthesis phase. Use of ALINT-PRO for functional verification on the early project stages makes the RTL design closure highly efficient. This application note gives a basic introduction on how to start working with ALINT-PRO, it familiarizes you with the major features of the product and helps to bring the GUI into use. Global Preferences and Project/File Properties
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